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• 眾所周知，深亞微米器件的整體尺寸和工作頻率在近幾年已經(jīng)得到了很大的突破。但是IC工程師們在基于0.25um及以下工藝進(jìn)行設(shè)計(jì)時，又不得不面臨一個新的問題，即占據(jù)整體芯片延時80％的互連線延時。本課程就是介紹基于0.25um及以下工藝的數(shù)字IC設(shè)計(jì)流程和實(shí)現(xiàn)流程以及ASIC設(shè)計(jì)物理版圖方面設(shè)計(jì)的技巧和方法。

  IC設(shè)計(jì)和版圖工程師們在使用0.25um及以下工藝進(jìn)行設(shè)計(jì)時不得不考慮新的設(shè)計(jì)方法。無論是前端的邏輯設(shè)計(jì)、綜合設(shè)計(jì)階段還是后端物理版圖實(shí)現(xiàn)，都要將目標(biāo)集中在設(shè)計(jì)收斂上（例如工作頻率，信號完整性和可制造性）。
  

  適合對象：
  ASIC 物理版圖工程師，IC邏輯設(shè)計(jì)工程師，系統(tǒng)設(shè)計(jì)工程師，產(chǎn)品工程師，應(yīng)用工程師，測試工程師，對IC設(shè)計(jì)和實(shí)現(xiàn)流程感興趣的經(jīng)理人，電子工程的在讀學(xué)生和IC制造工程師。

  內(nèi)容如下：
  

Part I:? Introduction on IC Design & Implementation
IC Design & Implementation Introduction
CMOS VLSI Manufacture & layout Process
IC Design Rules & Standard Cells
Part II: Introduction to IC Physical Design
Data Preparation for Layout Design
Floor-Planning
Pre-Rout
Placement
Clock Implementation
Scan Chain Optimization
Routing
Layout Verification
Part III (1): Parasitic, STA & Timing-Driven Layout
RC Parasitic
Layout Parasitic Extraction
Delay Models
Part III (2): Parasitic, STA & Timing-Driven Layout
Introduction to Static Timing Analysis
Timing Driven Placement/Routing & Timing Closure
Signal Integrity and Design Closure
Seminar Wrap-Up
Part IV: Layout Design Labs by ApolloII Place & Rout Tool
Lab1: Data Preparation: Create cell, load Tech. File, ref. Libs.
Lab2: Floor-planning, Power Mesh & Pre-Rout
Lab3: Std. Cell Placement & Optimization, Clock Tree Synthesis
Lab4: Report Timing, Routing & Optimization, Parasitic Extraction